本文提出一种异步时序电路设计的符号卡诺图的新方法。
Besides, the karnaugh map method and algebra method are presented for designing component level circuits.此外,本文提出元件级电路设计的卡诺图方法和代数方法。
This paper discusses the foundation and the application of reduced-dimension karnaugh map in numeral logical circuit design.文章介绍了在数字逻辑电路设计中降维卡诺图的建立和应用。